1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor memory and more particularly to a technology useful to connect the source/drain regions of two transistors to each other.
2. Description of the Background Art
Today, nonvolatile memories including EEPROMs (Electrically Erasable Programmable Read-Only Memories) are widely applied to, e.g., mobile telephones. An EEPROM, for example, allows only one bit of information to be stored in each storage cell transistor on the basis of whether or not a charge is present in its floating gate. However, to promote size reduction of the device, there should preferably be implemented the multiple-bit configuration of a cell transistor that allows two or more bits of information to be stored in the cell transistor.
While a multiple-bit transistor has been proposed in various forms in the past, I have paid attention to a multiple-bit transistor of the type including a silicon substrate formed with a plurality of grooves and floating gates formed on the side walls of the grooves. For details of this type of multiple-bit transistor, reference may be made to, e.g., Japanese patent Nos. 3249811 and 3249812.
In the multiple-bit transistor mentioned above, source/drain regions are formed on the bottoms of the grooves while a channel region is formed on the surface of the silicon substrate. The source/drain regions and channel region are therefore positioned at different levels from each other. This configuration is entirely different from the configuration of a typical MOS (Metal Oxide Semiconductor) transistor having both of source/drain regions and a channel region positioned on the surface of a substrate.
Generally, a semiconductor memory includes not only cell transistors but also select transistors for selecting the transistors or banks. The select transistors are usually implemented as MOS transistors. The source/drain regions of the cell transistors and those of the select transistors are connected together, so that any one of the select transistors selects the cell transistors or the bank connected thereto when turned on. However, the source/drain regions of the select transistors are formed on the surface of a substrate while the source/drain regions of the cell transistors are formed on the bottoms of grooves, as stated above. More specifically, the source/drain regions of such two different kinds of transistors differ in level from each other, i.e., do not lie in the same plane. Technically, therefore, connecting the source/drain regions of the two kinds of transistors to each other is difficult and has not been implemented yet.